Semiconductor devices, in particular field-effect controlled switching devices or components such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and an Insulated Gate Bipolar Transistor (IGBT) have been used for various applications including but not limited to use as switches in power supplies and power converters, electric cars, air-conditioners, and even stereo systems.
In such components, a load path between a first main electrode (also referred to as first load electrode, e.g., a source or emitter) and a second main electrode (also referred to as second load electrode, e.g., a drain or collector that are arranged opposite to each other in vertical devices) can be switched “ON” (i.e., the conductive state) or “OFF” (i.e., the blocking state) using an appropriate control signal applied to a control input (gate). In the conductive state, the load path has a low on-state resistance RON (between drain and source for a MOSFET, RDS(ON)). Typically, each new generation of controllable semiconductor components are desired to have a lower area specific on-resistance RON*A than the previous generation without deterioration of the switching characteristics. Thereby, on the one hand, the static power dissipation can be reduced, and on the other hand, higher current densities can be obtained.
For optimizing device operation, further figures-of-merit (FOM) may have to be taken into account. One important parameter is FOMoss (Figure-of-Merit (output)), i.e. the product of the on-state resistance RON and the output charge Qoss (stored charges in a space charge region formed in the OFF-state. As such, FOMoss weights conduction losses (RON) and switching losses (Qoss). A further measure for the overall performance and the costs for the gate-driver, respectively, of a component is FOMG (Figure-of-Merit (Gate)), i.e., the product of the on-state resistance RON (between drain and source for a MOSFET) and the gate charge QG.
For example, even for applications whose switching frequency (fsw) does not exceed 100 kHz, a high gate charge QG (due to the use of paralleled low RSD(ON)-MOSFET-cells) puts a lot of strain on the driver IC, as it dissipates most of these losses, which amount to QG*VG*fsw, where VG is the gate driving voltage. Because of power density requirements, layout challenges and/or timing issues, using more driver ICs is not often an option, whereas using better packages is costly and further requires additional cooling help from a printed circuit board (PCB). Note that handling the heat dissipation becomes harder with increasing fsw, since losses increase proportionally with fsw. This is e.g. particularly important for converters and rectifiers used in telecommunication.
Depending on application, low FOMG and/or low FOMoss are often desired to ensure a high overall performance of the component. However, so far used measures to reduce FOMoss and in particular FOMG tend to have side-effects on other device parameters.
For example, the gate charge QG of stand-alone gate trench structures (i.e. gate and field plate in different structure) may be reduced by increasing the gate oxide thickness. However, this tends to decrease the MOSFET performance, e.g. by enhancing increased DIBL (Drain Induced Barrier lowering).
In another example, a thick trench bottom oxide may be used. Although this lowers QG (in particular the gate-drain charge QGD), cost and complexity of the MOSFET are increased.
For these and other reasons there is a need for the present invention.